Phase locked loops are typically equipped with controlled oscillators, for example a voltage controlled oscillator (VCO). The VCO is coupled in a feedback loop in order to generate a high frequency clock from a low frequency reference clock. This reference clock is of a lower frequency since it is easier to generate various stable and precise clock signals at lower frequencies. An example of a phase locked loop according to the prior art is shown in FIG. 1. There is a VCO, a phase frequency detector PFD, a charge pump, a divider DIV and a compensation capacitor C1, an integrating analog element including a resistor R and a capacitor C2. The phase frequency detector PFD compares the phase of the reference clock REFCKL with the phase of the feedback clock signal SYSCLK which have basically the same clock frequency. The feedback clock signal SYSCLK is the clock signal PLLOUT output by the PLL and divided by the divider DIV. If the frequency or the phase of the feedback clock signal SYSCLK differs from the phase or frequency of the reference clock signal REFCLK, the charge pump CP applies a signal to the VCO in order to increase or decrease the phase or frequency of the output signal PLLOUT of the VCO. The signal ICH issued by the charge pump is a function of the difference between the reference clock REFCLK and the feedback clock signal SYSCLK.
The VCO may be implemented as a ring oscillator. The ring oscillator topology provides a series of cascaded delay stages (typically inverters). The output signal from the last delay stage is fed back to the input of the first delay stage. The total delay through the cascaded stages (including any net inversion of the signal within the system) is designed to satisfy criteria for sustained oscillation. Typically each delay stage has a variable delay governed by an independent input. The oscillation frequency of the VCO is then controlled by the input signal in order to vary the stage delay. The oscillation frequency for a ring oscillator can be tuned over a wide range, as for example 20% to 50% of the nominal center frequency of the VCO.
In order to comply with very low frequency of REFCLK signal, the PLL has to have a very low bandwidth. PLLs with such low bandwidths require external components (such as large capacitors) and also consume a lot of power. However, integrated circuits used in handheld and mobile devices require low power consumption and less number of external components while using as less chip area as possible. An alternate approach to implement such a low bandwidth PLL is for example described in the published German patent application DE 10 2010 048 584 and European patent application EP 11 183 369.5 filed Sep. 29, 2011 by the same applicant. In the latter patent application, the PLL described in this document uses semi-digital storage cells where a set of N number of semi-digital storage cells and 4 capacitors replace the loop filter capacitor C using much less chip area.